A high resolution graphics system is illustrated in FIG. 1. The graphics display system 10 of FIG. 1 comprises the CRT display 12. The pixels that are displayed on the screen of the CRT display 12 are stored in the frame buffer 14. A memory controller circuit 16 is provided for controlling the frame buffer 14. The memory controller includes an address generator 20. The address generator 20 receives the address of a pixel on the screen of the display terminal in terms of an x (horizontal or column) coordinate and a y (vertical or row) coordinate. The address generator 20 outputs a chip select signal, a row address signal, and a column address signal in order to address particular locations in the frame buffer 14.
Pixels at the addressed locations in the frame buffer 14 are transmitted via lines 21 to a CRT controller 22. The CRT controller 22 converts the pixels read from the frame buffer from digital to analog form and combines the pixels with CRT control signals including vertical and horizontal synchronization and blanking signals to form an image on the display 12.
The frame buffer 14 comprises a plurality of video RAMs (VRAMs). Currently available VRAMs are 64K*4, 256K*4 etc., which means there are 64K or 256K addressable memory locations, with each location having four bits.
In an illustrative example, the resolution of the CRT display 12 is 1280*1024. A 1280*1024 display system with a refresh frequency of 67 Hz has a pixel rate as high as 108 MHz. The pixel rate is related to the refresh frequency and may be defined as the rate at which pixels are read from the frame buffer.
The pixel rate reflects the time available to read pixels from the frame buffer and when the pixel rate is 108 MHz, the access time to the frame buffer is 9.5 ns/pixel.
Currently available VRAMs have an access time of about 35 ns/pixel. To achieve an average access time of 9.5 ns/pixel, it is necessary to have at least four sets of one or more VRAMs in order to output four pixels at the same time and reach the speed of 9.5 ns/pixel.
Conventionally, a frame buffer for a 1280*1024 display is formed from eight sets of VRAMs. The reason that eight sets of VRAMs are utilized, is that it is particularly easy to generate the address signals. Illustratively, each of the eight sets of VRAMs comprises one or more 256K*4 VRAMs. Each 256K*4 VRAM has 256K addressable locations which are arranged in 512.times.512 array. One such VRAM is schematically illustrated in FIG. 2. The VRAM 1 of FIG. 2 is shown as having row addresses (RAS) 0-511 and column addresses (CAS) 0-511.
Thus, to address the frame buffer, it is necessary to generate a chip select signal (CS) which selects the VRAM set, a row address select signal (RAS) which selects a row in the selected VRAM set, and a column address select signal (CAS) which selects a column in the selected row.
In the case where eight sets of VRAMs are utilized to form a frame buffer for a 1280*1024 resolution display, a pixel on the display with the coordinates x and y has the following address in the frame buffer
CS=x mod 8 PA1 RAS=y/2 PA1 CAS=y.sub.0 256+x18 (0 bit of the y coordinate multiplied by 256 added to the result of the x coordinate divided by 8). PA1 CS=bit 9 to bit 11 of the x coordinate PA1 RAS=y coordinate PA1 CAS=first eight bits of the x coordinate. PA1 CS=x mod 5 PA1 RAS=y/2 PA1 CAS=y.sub.0 *256+x/5.
These addresses are particularly easy to generate because they only involve division by powers of two which is easily accomplished by shifting an appropriate number of bits to the right.
FIG. 3 shows how the pixels from one row of the display are organized in the eight sets of VRAMs.
As indicated above, each VRAM stores four bits at each address location. However, in many graphics systems each pixel is represented by more than four bits. In this case each of the eight sets contains a plurality of 256K VRAMs connected so that within each set bits from the same pixel are stored at corresponding addresses. For example, in a graphics system with 24 bits per pixel, each of the eight sets of VRAMs contains six VRAMs, each of which stores four bits at each address location. Thus, when a given RAS or CAS are transmitted to one of the VRAM sets 24 bits are read out, four bits from each of the six VRAMs in the set.
The problem with forming a frame buffer from eight sets of VRAMs is that memory capacity is not utilized efficiently. Specifically, the eight sets of VRAMs are only 62.5% full because there are only 1280*1024 pixels and 8*256K address locations. This under-utilization of memory capacity is a very serious problem in graphics system because the memory constitutes a significant fraction of the cost of the overall system.
Another conventional architecture for a frame buffer is to use linear addressing and 64K*4 VRAMs. Specifically, five sets of 64K VRAMs are utilized as shown in FIG. 4. The first pixel up to the 256.sup.th pixel of each display row is stored in the first set, the 257.sup.th pixel up to the 512.sup.th pixel of each row is stored in the second set. The same applies to the rest of the VRAM sets until the 1025.sup.th -1280.sup.th pixels are stored in the fifth set.
In this architecture, it is also very easy to generate the address signals which are as follows:
Furthermore, this architecture also makes full use of all memory units. However, the linear address method can only access one address (i.e., one pixel) at a time. As the speed of VRAM is slow, it cannot meet the desired pixel rate of 9.5 ns/pixel. A solution to this problem is to add a temporary buffer between the frame buffer and the CRT controller (see FIG. 1) to compensate for the slow speed of the VRAMs and the high pixel rate required by the CRT controller. However, the use of the temporary buffer is a shortcoming of this architecture because it significantly adds to the overall system cost.
In view of the foregoing, it is an object of the present invention to provide an alternative memory architecture for the frame buffer of a high resolution graphics system. In particular, it is an object of the invention to provide a memory architecture which makes full use of available memory capacity, meets the desired pixel access speed, and requires only simple circuitry for the generation of address signals.
More specifically, it is an object of the present invention to provide a divide-by-five circuit which can be used to implement such a memory architecture.